• 32/64-bit, +3.3V, PCI/PCIX-based PWB
  • Available in configurations with up to five VirtexII FPGA's (FF1152 BGA)
  • Available with 2V6000/2V4000/2V8000
  • Four 512kx36 Sync Burst SRAM's
  • One 72-bit SDRAM DIMM (product ships with a 1Gbyte SDRAM DIMM)
  • Tightly interconnected FPGA's facilitate the partitioning process
• Flexible, abundant and configurable embedded memory in FPGA's:
  • Up to 1620 Kbytes dual-port Block SelectRAM (assuming 5 XC2V6000)
  • Up to 660 Kbytes Distributed SelectRAM (assuming 5 XC2V6000)
  • Direct support for TDM interconnect multiplexing
• Support for Mentor Graphics's SpeedGate DSV (a partitioning tool)
  • SpeedGate DSV partitioning files available
• 10A on-board switching regulator for both +3.3V and +1.5V (Only requires +5V power)
• Standalone operation via separate power connector
• Status LED's provide instant status and operational feedback
• Fast/Easy FPGA configuration via standard SmartMedia FLASH card
  • Microprocessor controlled (ATmega128L)
  • RS232 port for configuration/operational status and control
  • Fastest possible configuration using SelectMap
  • Five 2v6000's configures in less than 5 seconds
  • Sanity checking programs for bit files simplify the configuration process
• 5 low skew clocks distributed to all FPGA's and headers (from up to 8 possible sources):
  • 2 socketed oscillators
  • PCI Clock
  • 1 clock dividable via CPLD
  • 4 external clocks via ribbon cable (may be differential!)
• 2 CY7B993/4 RoboClockII PLL's
• 2 3807 Clock Drivers
• 8 low speed clocks connected between all FPGA's and headers
• Robust observation/debug with 400+ connections for logic analyzer observability and pattern generator stimulus
• Custom daughter PWB for application specific circuitry and interfaces

• Product Brief - PDF[HI - 3.0MB][LO - 397KB]
• Concise Data Sheet [PDF - 796KB]
• Frequently Asked Questions [PDF - 167KB]
• Processor and CPLD update (3/4/03) [ZIP - 185KB]
• Stuffing Options Comparison [PDF - 43KB]
• Board Diagram [PDF - 22KB]
• Top-down view with dimensions [PDF - 299KB]
• User's Manual [PDF - 8.3MB]
• PowerPoint Summary [PPT - 697KB]
• Bitstream Encryption :
  • Using Encrypted Bitstreams [PDF - 49KB]
  • Xilinx Encryption Bug White Paper [PDF - 62KB]
• VirtexII FPGA Family
  • Datasheet [PDF - 2.4MB]
  • Handbook [PDF - 16.0MB]
  • 2v6000ES Errata [PDF - 26KB]
  • 2v6000 Errata [PDF - 61KB]
  • 2v8000 Errata [PDF - 68KB]
• Berg 200-pin connector (on daughter card) Datasheet [PDF - 199KB]
• Berg 200-pin connector (on DN3000k10) Datasheet [PDF - 269KB]
• Datasheet for SSRAM installed
  • Micron 18Mb SyncBurst SRAM [PDF - 670KB]
  • Samsung K7A163600A[PDF - 349KB]
• AETEST Utility & USB Controller
• DN3000K10 Errata [PDF - 60KB]
• Clock Frequency Calculator [EXE - 1.7MB]
• HyperTerminal File [HT - 10KB]
• Daughter Card Compatibility Guide [PDF - 65KB]
• 200-pin Header Connection Summary [XLS - 2.7MB]

DN3000K10
ASIC Prototyping Engine

The DN3000k10 is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN3000k10 can be either hosted in 32/64-bit PCI/PCIX slot, or used in a stand-alone environment. A single DN3000k10 configured with five 2V6000's can emulate up to 3 million gates of logic as measured by LSI. The DN3000k10 achieves high gate density and allows for fast target clock frequencies by utilizing up to five FPGA's from Xilinx's VirtexII family for logic and memory. High I/O-count, 1152-pin, flip-chip BGA packages are employed providing for abundant, fixed interconnect between FPGA's. A total of 400+ test pins are provided on the top of the PWB for logic analyzer-based debugging, or for pattern generator stimulus. Custom daughter cards can be mounted to these connectors as a means to interface the DN3000k10 to application-specific circuits. A reference 32-bit PCI target design and test bench are provided (in Verilog and VHDL) at no additional cost.

Easy Configuration via SmartMedia
The configuration bit files for the FPGA's are copied onto a 32-megabyte SmartMedia FLASH card (provided) and an on-board ATmega128L microprocessor controls the FPGA configuration process. Visibility into the configuration process is enhanced with an RS232 port. Sanity checks are performed automatically on the configuration bit files, streamlining the configuration process. Quick FPGA configuration occurs at the fastest possible SelectMap frequency - 48MHz. Eight LED's provide instant status and operational feedback. Two of these LED's are connected to the CPLD and can be user-configured.

Among several electronic hardware and software design solutions, Mentor Graphics is a world leader in verification solutions. We recommend their cost-effective SpeedGate DSV tool for partitioning, debug, and mapping to our DN3000K10 boards with multiple FPGAs.

To add Gigabit Ethernet capabilities to this board, we recommend the MP1000TX Gigabit Ethernet Daughter Board from Metanetworks.

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