- PCI Express (8-lane) logic prototyping system with 2-6 Altera Stratix3 FPGA's
- EP3SL340-4, -3, -2(slowest to fastest)
- -FF1760 package: 1,120 I/O's
- Fixed 8-lane PCIe interface and controller provided
- PCIe GEN1 rev 1.1 shipping now
- PCIe GEN2 coming in Q3'2008(4-lane only)
- Easy PCIe core prototyping with our exclusive PCIe PIPE Slowdown Core
- 15+ million ASIC gates (ASIC measure) when stuffed with 6 Stratix3 3SL340's
- FPGA to FPGA interconnect is a mix of single-ended or LVDS
- 600Mhz LVDS chip to chip (1.2 Gb/s)
- LVDS pairs can be used as two single-ended signals at reduced frequency (~225MHz)
- Reference designs for integrated I/O pad ISERDES/OSERDES
- 10x pin multiplexer per LVDS par
- Greatly simplified logic partitioning
- Source synchronous clocking for LVDS
- Main Bus(MB) connects all Stratix3 FPGA's (96 signals)
- Auspy models for partitioning assistance
- 4 separate DDR2 SODIMMs (250MHz)
- Direct connection to FPGA's A,C,F,D
- 64-bit data width, 250MHz operation
- PC2-4200 or better
- Addressing/power to support 4GB in each socket
- DDR2 Verilog/VHDL reference design provided (no charge)
- DDR2 SODIMM data transfer rate: 32Gb/s
- Alternate pin compatible memory cards available (consult factory for availability):
- SRAM: QDR, ASYNC, STD, or PSRAM
- FLASH
- DRAM: SDR, DDR1, PSRAM, RLDRAM or DDR3
- Mictor, USB PHY, Extra Interconnect
- SODIMM Daughtercard expansion
- Seven independent low-skew global clock networks
- G0, G1, G2, M48, EXT0, EXT1, REF
- Three, high-resolution, user-programmable synthesizers for G0, G1, G2
- User configurable via CompactFLASH, USB, and/or PCIe
- All seven global clocks networks distributed differentially and balanced
- Two independent single-step clocks
- Seven independent external clocks inputs (single-ended or differential) can be injected onto low-skew global clock networks
- Flexible customization via daughter cards
- 3 daughter card locations: FPGA’s D,E,F
- 400-pin FCI MEG-Array connectors
- 93 LVDS unidirectional pairs + clocks (or 186 single-ended)
- 450MHz on all signals with source synchronous LVDS
- Signal voltage set by daughter card (1.2v to 3.3V)
- Reset
- Supplied power rails (fused):
- +12v (24W max)
- +5V (10W max)
- +3.3V (10W max)
- Pin multiplexing to/from daughter cards using LVDS (up to 10x)
- Fast and Painless FPGA configuration
- CompactFLASH, USB, PCIe, JTAG
- Configuration Error reporting
- Accelerated configuration readback
- RS232 port for embedded uP debug
- Accessible from all FPGA’s via separate 2-signal bus
- Full support for embedded logic analyzers via JTAG interface
- SignalTap, and other third-party debug solutions
- 54 status FPGA-controller LED’s: enough illumination to decontaminate minimally processed vegetables
- DN7006k10PCIe-8T product datasheet [HI - 4.0MB]
- DN7006k10PCIe-8T product datasheet [LO - 862KB]
- DN7006k10PCIe-8T Single-ended Block Diagram [PDF - 1.03MB]
- DN7006k10PCIe-8T LVDS Block Diagram [PDF - 1.07MB]
- PCIE8T Interface User Manual [PDF - 71.5KB]
- MEG Array Daughter Card Interface Description [PDF - 660KB]
- Daughter Card Compatibility Guide [PDF - 63KB]
- Dini Group Mainbus Specification [PDF - 167KB]
- Dini Group USB Specification [ZIP - 180KB]
- Downloads Page
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DN7006K10PCIe-8T
ASIC Prototyping Engine featuring Altera Stratix3
Hosted via 8-lane PCI Express
Overview
The DN7006k10PCIe-8T is a complete logic prototyping system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN7006k10PCIe-8T is hosted in an 8-lane PCIe bus (GEN1), but can be used stand-alone and configured via USB and/or Compact FLASH. A single DN7006k10PCIe-8T configured with 6 Altera Stratix3, 3SL340's can emulate up to 15 million gates of logic as measured by a reasonable ASIC gate counting standard and this number does not include embedded memories and multipliers resident in each FPGA. One hundred percent (100%) of the 3SL340's FPGA resources are available to the user application. The DN7006k10PCIe-8T achieves high gate density and allows for fast target clock frequencies by utilizing the largest FPGA from Altera's Stratix3 family. Any subset of FPGA's can be stuffed and we can acommodate any combination of speed grades.
Stratix3 FPGAs from Altera
The DN7006k10PCIe-8T uses high I/O-count, 1760-pin, flip-chip BGA packages. The 3SL340 has 1,120 I/O's and all are utilized. Abundant fixed interconnects (either differential or single-ended) are provided between the FPGA's. Where possible, FPGA to FPGA busses are routed and tested LVDS, run at 600MHz+ (which is 1.2 Gb/s if used in DDR mode). Single-ended at the reduced speed of 225 MHz is characterized and tested. Example designs utilizing the integrated I/O shift registers with DDR for pin multiplexing are included. A 96-pin main bus (MB) is connected to all FPGAs including the configuration FPGA. The connection to the configuration FPGA allows for data movement via USB to any/all FPGA's.
Dedicated PCIe, 8-lane controller and exclusive IP for slowdown of PIPE interface
We ship the DN7006k10PCIe-8T with a full function, fixed, 8-lane master/target. Drivers and 'C' source for several operating systems are included at no cost. Easy PCIe core prototyping with our exclusive PCIe PIPE Slowdown Core
Specs of FPGAs Avaliable on the DN7006k10PCIe-8T
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