• FCI MEG-Array based daughter card enables 8-lane PCIe hosting of DINI ASIC Emulation products
    • Used in combination with the DNMEG_CBL-U and DNMEG_CBL-D
    • PCIe complaint iPASS connectors and cables
    • 3ft to 18ft cabling (1M to 6M)
  • 8-lane PCI Express daughter card with Xilinx Virtex-5 FPGA
  • PCIe hosting of DINI ASIC emulation products (with DNPCIe_CBL-D)
  • PCIe peripherals to DINI ASIC emulation products (with DNPCIe_CBL-U)
  • Emulation of PCIe to PCIe bridges
    • Dual 1/4/8-lane PCIe to 1/4/8-lane PCIe bridge
    • Triple 1/4/8-lane PCIe bridge
  • Xilinx Virtex-5 LX110 (FF1513) with 670k+ ASIC gates (LSI measure)
    • 100% FPGA resources available for user application
    • PCIe controller
    • DDR2 interface
  • Genesys Logic GL9714 PCI Express Physical Interface (PCIe GEN1 rev 1.1)
    • Standard 250MHz or 125MHz PIPE interface between PHY and FPGA
    • Support for emulation of power down states P0, P0s, P1, P2
  • 400-pin MEG-Array (FCI)
    • 93 LVDS pairs + clocks (or 192 single-ended)
    • Host interconnect is single-ended or LVDS
    • 450MHz on all signals with LVDS (900Mb/s with DDR)
    • Reset, presence detect
    • Supplied power rails (fused):
      • +12V (24W max)
      • +5V (10W max)
      • +3.3V (10W max)
    • Reference designs for integrated I/O pad ISERDES/OSERDES
    • 10x pin multiplexing per LVDS pair
    • Source synchronous clocking
  • DDR2 SODIMM (250MHz)
    • 64-bit data width, 250MHz operation
    • PC2-5300
    • Addressing/power to support 4GB
    • DDR2 Verilog/VHDL reference design provided (no charge)
    • DDR2 SODIMM data transfer rate: 32Gb/s
    • Alternate pin compatible memory cards available:
      • QDR SSRAM, Mictor, RLDRAM, SSRAM, DDR3, interconnect, SDRAM DRAM, FLASH, and others
  • FPGA configuration via on-board FLASH
  • RS232 port for embedded uP debug
  • Mictor for logic analyzer debug
  • Battery socket for configuration bitfile encryption
  • Full support for embedded logic analyzers via JTAG interface
    • ChipScope, ChipScope Pro and other third-party debug tools
  • Enough light from 16 status LED’s to frighten children with shadow puppetry.

  • Block Diagram [PDF - 3.07MB]
  • Manual [PDF - 1.15MB]
  • Product Brief [PDF - 124KB]
  • DNMEG_CBL Product Manual [PDF - 325KB]
  • MEG Array Daughter Card Interface Description [PDF - 660KB]
  • Daughter Card Compatibility Guide [PDF - 63KB]
  • Downloads Page

 

DNMEG_CPCIe
Daughtercard form-factor
Virtex-5 Based
PCIe Daughter Card with iPASS

Overview

The combination of the DNMEG_cPCIe, the DNPCIe_CBL-U/D, and two iPASS cables adds 1-lane, 4-lane, or 8-lane PCI Express (GEN1) to all DINI Group products that have FCI MEG-Array expansion connector.

Virtex-5 LX110 FPGA from Xilinx

The DNMEG_cPCIe uses a Xilinx Virtex-5 LX110 in a FF1153 flip-chip BGA to host the PCIe controller. The LX110 has 69,120 flip-flops and 576 kbytes of block memory – plenty of resources for a feature packed 8-lane PCIe controller. Two Genesys Logic GL9714 PHY devices provide the PCI Express cable interface. Virtex-5 GTP "RocketIO" is not used in this approach.

Memory

A single DDR2 SODIMM socket is connected to the LX110 FPGA. The socket is tested to 250MHz with a PC2-5300 DDR2 SODIMM. Standard, off-the-shelf DDR2 memory DIMM’s (PC2-5300) work nicely and we can provide 512MB or 1GB versions for a small charge. The larger 2GB version is available, but not at a small charge. As with all DDR2 SODIMM sockets on DINI products, we have alternative SODIMM’s that can be stuffed into these positions. Consult the factory for more details, but the list includes DDR3, FLASH, SSRAM, QDR SSRAM, RLDRAM, SDR SDRAM, mictors, interconnect, and others.



DNMEG_CPCIe, top side


DNMEG_CPCIe, bottom

Note: Product comes with iPASS 4-lane PCIe cable cages on connectors, not shown in pictures.


DNPCIe_CBL Downstream, recommended accessory


DNPCIe_CBL Upstream, recommended accessory


DNPCIe_CBL Upstream connected to DNPCIe_CBL Downstream, recommended accessory