• Daughter Card with Xilinx Virtex-5T FPGA (FF1136)
    • LX50T, SX50T, LX85T, SX95T or LX110T
    • SX95T, FX100T, LX155T (with manual JTAG configuration)
  • 100% FPGA resources available for user application
  • Nearly 660k ASIC gates (LSI measure) with LX110T
  • DDR2 SODIMMs (250MHz)
    • 64-bit data width, 250MHz operation
    • PC2-3200/PC2-4200
    • Addressing/power to support 4GB in each socket
    • DDR2 Verilog/VHDL reference design provided (no charge)
    • DDR2 SODIMM data transfer rate: 25.6Gb/s
    • Alternate pin compatible memory cards available (consult factory for availability):
      • QDR SSRAM, FLASH, SSRAM, RLDRAM, Mictor, USB PHY, et al.
  • Flexible, abundant clock resources
    • 3 board-level clocks configurable clocks based on the Si5326
    • 2 stuffable low-jitter fixed oscillators
    • 2 external differential clock inputs
  • Mount to DINI products with 400-pin MEG-Array connectors
    • 93 LVDS pairs + clocks (or 186 single-ended)
    • 450MHz on all signals with LVDS (slower when used single-ended)
    • Reset, presence detect
    • Pin multiplexing to/from motherboard using ISERDES/OSERDES and LVDS (up to 10x)
  • Fast and Painless FPGA configuration with integrated EEPROM
  • RS232 port for embedded uP debug
  • Full support for embedded logic analyzers via JTAG interface
    • ChipScope, ChipScope Pro and other third party solutions
  • Enough status LED’s to befuddle an armadillo
  • Gigabit serial I/O interfaces using GTP transceivers:
    • 4 Small form factor (SFP) modules
      • 1x, 2x, 4x Fibre Channel
      • 1G Ethernet
      • XAUI
    • SMA connectors for off-board cabling to 4 TX/RX channels
      • PCI Express
      • SATA
      • Serial RapidI/O
      • Aurora
    • Samtec QSE connector for off-board cabling of channels of rocketI/O
      • LX110T and SX95T only
    • Infiniband connector
    • Clocking options for standard serial communication protocols
    • Ability to use embedded Ethernet MAC with SFP and SMA connectors.

  • Block Diagram [PDF - 3.0MB]
  • Product Brief [PDF - 544KB]
  • User's Manual [PDF - 1.84MB]
  • MEG Array Daughter Card Interface Description [PDF - 660KB]
  • Daughter Card Compatibility Guide [PDF - 63KB]
  • Downloads Page

 

DNMEG_V5T
Daughtercard form-factor
Virtex-5T Based
ASIC Prototyping Engine

The DNMEG_V5T enables engineers a vehicle to utilize the Xilinx Virtex-5T FPGAs. The DNMEG_V5T is hosted on any DINI Group ASIC Emulation product that has MEG-Array expansion capability. Stand-alone operation is supported with a separate power supply. The DNMEG_V5T is factory stuffed with one of the Xilinx Virtex-5T FPGAs from the following list: LX50T, SX50T, LX85T, SX95T or LX110T. These devices come in speed grades -1, -2, -3 (slowest to fastest). The largest device, the LX110T contains 69k flip-flop/LUT pairs and can emulate >660kgates of logic as measured by LSI. The SX95T is about 15% smaller in terms of FF/LUT pairs, but contains more internal memory and 10 times the number of DSP48E slices. A high I/O-count, 1136-pin, flip-chip BGA package is employed, providing for abundant interconnects to the host and assorted peripherals. 100% of the FPGA’s resources are available to the user’s application. One DDR2 SDRAM SODIMM is provided, allowing the FPGA to address up to 4GB of memory. Alternative SODIMM’s are available, including QDR SSRAM, FLASH, Mictor, RLDRAM, USB PHY, et al. The DDR2 SODIMM socket is tested at 250MHz, and reference designs are provided. A total of 186+ test pins (plus clocks and power) are provided on the top and bottom of the PWB via a 400-pin MEG-Array expansion connector. When used in LVDS mode (93 pairs), this interface is capable of running 450MHz to/from the host board.

All 16 high-speed transceiver channels (GTP’s) are utilized. Four GTP channels are connected to SPF sockets, enabling a vast list of third party physical layer interfaces. Four channels are connected to SMA’s. Four channels are connected to an Infiniband connector. When an LX110T or SX95T is stuffed, an additional 4 GTP channels are available via a QSE connector. All channels are tested and characterized to 3.75Gbps, with higher frequencies later when Xilinx announces the V5 ?XT FPGAs in ‘08.

Multiple LED’s provide instant status and operational feedback. Although no animal testing was performed, statistical models are showing the 8 LED’s provide enough illumination to irritate and possibly befuddle an armadillo.

As always, reference material such as DDR SDRAM controllers, flash controllers, and PowerPC code is included (in Verilog, VHDL, C) at no additional cost.


Specs of FPGAs Avaliable on the DNMEG_V5T