The Dini Group

8-lane PCI Express daughter card with Xilinx Virtex-5 FPGA (GEN1 and GEN2)

LX50T, LX85T, LX110T, SX50T, FX70T (-1, -2, -3)
with manual configuration via JTAG (or bitstream compression)

LX155T, SX95T, FX100T (-1, -2, -3)

1, 4, or 8-lane PCIe hosting of DINI ASIC emulation products (with DNMEG_CBL-D)
1, 4, or 8-lane PCIe peripherals to DINI ASIC emulation products (with DNMEG_CBL-U)
Emulation and prototyping of PCIe SOC/IP:
- PCIe to PCIe bridges (GEN1 and GEN2)
- PCIe to 1000Base-T, 100Base-T, or 10Base-T
- PCIe to Fibre Channel
- PCIe to SAS/SATA
- PCIe to Inifiniband
(Optional) PCIe clock slow down IP

Allows clocking the PIPE interface as slowly as 35 MHz

Fixed PCIe controller provided

Master-moding with drivers included
100% FPGA resources available for user application if fixed PCIe controller not used

Nearly 660k ASIC gates (LSI measure) with LX110T

Add up to 32 million ASIC gates with the DN9000k10

DDR2 SODIMMs (250MHz)

64-bit data width, 250MHz operation
PC-3200/PC2-4200
Addressing/power to support 4GB in each socket
DDR2 Verilog/VHDL reference design provided (no charge)
DDR2 SODIMM data transfer rate: 25.6Gb/s
Alternate pin compatible memory cards available (consult factory for availability):
- QDR SSRAM, FLASH, SSRAM, RLDRAM, Mictor, USB PHY, DDR3 et al.

Flexible, abundant clock resources

3 board-level clocks configurable clocks based on the Si5326
2 stuffable low-jitter fixed oscillators
Fixed 100MHz and 200MHz oscillators

For PCIe and DDR2 clocking

Off-board differential clocking

Mount to DINI products with 400-pin MEG-Array connectors

93 LVDS pairs + clocks (or 186 single-ended)
450MHz on all signals with LVDS (slower when used single-ended)
Reset, presence detect
Pin multiplexing to/from motherboard using ISERDES?OSERDES and LVDS (up to 10x)
Supplied power rails (fused):

+12V (24W max)
+5V (10W max)
+3.3V (10W max)

Reference designs for integrated I/O pad ISERDES/OSERDES
Source synchronous clocking

Fast and Painless FPGA configuration with integrated PROM
RS232 port for embedded uP debug
Mictor for logic analyzer debug
Battery socket for configuration bitfile encryption
Full support for embedded logic analyzers via JTAG interface

ChipScope, ChipScope Pro and other third party solutions

Enough status LED's with which to pull over a speeding Porsche
Gigabit serial I/O interfaces using GTP transceivers:
- 1 Small form factor (SFP) modules
- SMA connectors for off-board cabling to 4 TX/RX channels
- iPASS for x1, x4, x8 PCI Express cabling
- Clocking options for standard serial communication protocols
- Ability to use embedded Ethernet MAC with SFP and SMA connectors
- DisplayPort (x4)

Block Diagram [PDF - 324KB]
User's Manual [PDF - 1.91MB]
Datasheet [PDF - 410KB]
MEG Array Daughter Card Interface Description [PDF - 660KB]
Daughter Card Compatibility Guide [PDF - 63KB]
Downloads Page

DNMEG_V5T_PCIE
Daughtercard form-factor
Virtex-5T Based
ASIC Prototyping Engine

The DNMEG_V5T_PCIE is a daughter that adds a PCI Express interface to the many FPGA ASIC prototyping boards from The DINI Group. The PCIe interface can be configured as 1, 4, or 8-lanes. When using Xilinx Virtex-5 LXT or SXT devices, the board is fully compatible with 2.5Gb/s GEN1 PCIe. Gen2 (5.0Gb/s) PCIe functionality is fully supported using the Virtex-5 FX70T-2 (or FX100T-2). When used as a daughter card to the DN9000k10PCIe-8T, an 8-lane PCIe <-> PCIe bridge can be emulated with either (or both) sides GEN1 or GEN2. A treble PCIe bridge can be constructed with two of these daughter cards. The massive 32 million gate DN9000k10 can be converted to a high data bandwidth PCIe master (or peripheral).

A full featured PCIe controller is provided standard. The controller includes master moding DMA. 'C' source examples along with drivers are included.

The DNMEG_V5T_PCIE mounts to a DINI base-board using the 400-pin FCI MEG-Array expansion connectors. A small PCIe buffer card (DNMEG_CBL-D or DNMEG_CBL-U) is inserted into a host/peripheral PCIe slot and the DNMEG_V5T_PCIE is connected via two, 4-channel iPASS cables. The DNMEG_V5T_PCIE can be used stand-alone.

Xilinx Virtex-5 FPGA

In its standard configuration, the DNMEG_V5T_PCIE is stuffed with a Xilinx Virtex-5 LX110T-1. The LX110T is a relatively large FPGA, containing 69,120 LUT/FF pairs, along with 64, 25x18 multipliers. Five megabytes of internal block memory (296, separate 18kbit blocks) enable the implementation of large scratchpad memories and FIFO's - vital for PCIe applications. The Virtex-5 family has 6-input lookup tables (LUTs), making this FPGA family extremely logic rich. The larger LUT works to reduce the number of logic layers which increases the frequency of operation. Optional stuffing options include the SX50T, which has a greater number of embedded multipliers and is optimized for DSP-type applications.

The configuration PROM is a XCF32P, which means the bit files for a LX50T, LX85T, LX100T, FX70T, and SX50T can be stored allowing FPGA configured seamlessly at power up. This product can be stuffed with the FX100T, LX155T, or the SX95T, but the bit files are too large for the XCF32P. These devices require manual FPGA configuration at power-up via JTAG. With compression, we think the configuration file for the SX95T might fit.

RocketI/O GTP

Eight of the RocketI/O GTP transceivers are used for the 8-lane PCIe interface (via the iPASS cables). Four of the channels are connected to SMA connectors (16 SMA connectors total). The SMA connectors can be used to create a large list of high speed serial interfaces. The most common is Infiniband. A DisplayPort physical interface is added when this board is stuffed with the LX110T or FX70T (SX95T, LX155T). Four RocketI/O GTP channels are needed. An SFP socket shares a RocketI/O GTP with DisplayPort. A wide range of SFP modules is available. The list includes, but not limited to, 10/100/1000Base-T, SATA, Fibre Channel. The SMA's along with DisplayPort/SFP enable all sorts of PCIe bridges to be emulated: PCIe <-> SATA, PCIe <->1000BaseT, etc.

Memory

A single DDR2 SODIMM socket is connected to the FPGA. This SODIMM socket is tested to 250MHz with a DDR2 SODIMM. Standard, off-the-shelf DDR2 memory DIMM's (PC2-5300) work nicely and we can provide these for a small charge. We have developed alternative SODIMM's that can be stuffed into these positions. Consult the factory for more details, but the list includes FLASH, SSRAM, QDR SSRAM, RLDRAM, SDR SDRAM, mictors, DDR1, DDR3, interconnect, and others. The board includes a DDR2 controller in VHDL and Verilog, and example RocketIO implementations in Verilog, with VHDL available on request.

Other Features

A Mictor with 28 FPGA connections enables debugging with Tektronix or Agilent Logic Analyzer. Eight user LED's can be used for all sorts of FPGA-controller visual feedback. The LED's are bright enough to pull over speeding exotic cars if sequenced correctly. This law enforcement application has not been completely tested.

Specs of FPGAs Avaliable on the DNMEG_V5T_PCIe